The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, as IC technologies are continually progressing to smaller technology nodes, such as 65 nm technology node, 45 nm technology node, 20 nm technology node and below, simply scaling down similar designs used at larger feature sizes often results in poorly shaped or poorly arranged device features. Typically, optical proximity correction (OPC) may be performed on a design pattern before the pattern is created on a mask. However, current OPC techniques may not offer great enough fidelity or sufficient rules to correct problems in sub-45 nm designs. Therefore, although existing methods for improving IC manufacturing have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.